Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. An FPGA may also include various dedicated logic circuits, such as memories, digital clock managers (DCMs), and input/output (I/O) transceivers. An FPGA may include one or more embedded processors. The programmable logic of an FPGA (e.g., CLBs, IOBs, and interconnect structure) is typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells. The states of the configuration memory cells define how the CLBs, IOBs, interconnect structure, and other programmable logic are configured. Some FPGAs include support for run-time partial reconfiguration, which provides the ability to alter the behavior of portions of a circuit configured in an active FPGA. Partial reconfiguration is useful in systems that must support a wide range of optional behavior, such as performance optimization, only a subset of which is operational at any point in time.
To implement a circuit design using an FPGA, the design is synthesized and mapped onto programmable logic blocks, placed within the FPGA, and routed using the programmable fabric. The place and route phases of implementing a circuit design engage generating a layout of the circuit elements on the FPGA and defining the routing resources that connect the elements. In some instances, it may be necessary to modify a design after the design is physically implemented in order to meet a particular design criteria. In an example, the design criteria may be reduced power consumption and/or performance optimization. Current methods for implementing design changes such as power optimization are inefficient in terms of CPU runtime and/or in the quality of the results. For example, after making a change to a design, a designer may have to completely re-implement the physical design from scratch. Such a technique, however, is not runtime efficient. Alternatively, a designer may employ strict guiding methods that may improve runtime, but often provides results of poor quality that does not meet the overall design goal. Accordingly, there exists a need in the art for an improved method and apparatus for implementing a modified version of a previously implemented circuit design.